The present invention relates to a voltage regulator for electrically programmable non-volatile semiconductor memory devices.
More specifically the present invention relates to a voltage regulator of the type comprising a gain stage supplied by a programming voltage and having an input terminal connected to a divider of the programming voltage and an output terminal connected to a programming line of at least one memory cell.
As known an individual non-volatile memory cell comprises an MOS transistor in which the gate electrode located over the channel region is floating, i.e. displays high continuous impedance to all the other terminals of the same cell and of the circuit in which the cell is inserted.
The cell also includes a second electrode, called a control gate, which is piloted through appropriate command voltages. The other electrodes of the transistor are the usual drain, source and body terminals.
By applying appropriate voltages to the cell terminals it is possible to change the charge quantity present in the floating gate, e.g. utilizing known Fowler-Nordheim Tunnelling and/or Channel Hot Electron Injection phenomena. This allows placing the transistor in two logic stages: a first state with "high" threshold voltage and a second state with "low" threshold voltage.
If a voltage is applied at the control gate which is intermediate between these two values, it is possible to "read" the state of the transistor since it displays between the drain and source terminals a low or high impedance depending on the threshold voltage value. Therefore the transistor can be considered a logic memory element.
Since the floating gate presents a high impedance toward any other cell terminal, the charge stored therein can persist for an indeterminate time even if supply is removed from the circuit in which it is inserted. The cell therefore displays non-volatile memory characteristics.
The operation by which the charge is stored in the floating gate is termed "programming" while the operation by which the charge is removed from the floating gate is termed "erasure".
Generally a non-volatile memory circuit integrated on a semiconductor comprises a multiplicity of cells of the above type organized in rows (parallel to "word line" conductors) and columns (parallel to "bit line" conductors). The cells belonging to a given row share a word line which is connected to pilot all of their respective control gates, while the cells belonging to a given column have their drain terminals all connected together.
It is also known that non-volatile memory cells and in particular the FLASH type require accurate control of drain voltage Vd during the programming phase, i.e. the voltage applied on the bit line. The drain voltage must indeed satisfy several conditions listed below:
It must be high enough to allow fast cell programming, PA1 it must be at the same time low enough to avoid the so-called "soft-erasing" phenomenon, which consists of partial erasure of the cell or degradation of the characteristics of the cell with use, and PA1 for reliability reasons it must always be such as to avoid setting off the phenomenon known as "parasitic-bipolar" operation.
The optimal range for such a voltage is in general rather small and typically between 5 and 6 volts.
It is noted also that the conditions indicated above are variable depending on the production process and in particular depending on the length of the memory cell. The production processes indeed lead to variations in the dimensions of the cells and in particular of the polysilicon layers and this represents one of the critical parameters in production.
Taken all together the above observations lead to the conclusion that it is necessary to equip the memory circuit with a particularly refined and accurate voltage regulator to supply the correct voltage to the bit line in the programming phase.
The known art already proposes some solutions to meet this requirement.
In general since the voltages supplied from the outside to the memory circuit are substantially two and in particular a 5 V supply voltage Vcc and a 12 V programming voltage V.sub.PP, control of drain voltage is normally achieved by division of the programming voltage V.sub.PP.
In this manner there is achieved a drain voltage relatively stable as concerns temperature and the circuit production process parameters and variable by .+-.5% with the programming voltage V.sub.PP.
In the annexed FIG. 1 is shown schematically a first circuit solution of known type provided by utilizing division of the programming voltage.
The voltage regulator shown in FIG. 1 comprises a resistive divider consisting of three resistances R1, R2, R3 connected between the programming voltage line V.sub.pp and ground. In parallel with the resistances is a group of four MOS transistors connected in series with each other through their respective source and drain terminals.
The gate terminals of the first transistor M1 and fourth transistor M4 are connected between the first and second resistances and between the second and third resistances.
The voltage applied to the bit line is taken on the gate terminal of the second transistor M2 which is inserted in the circuit in diode configuration with gate and drain short-circuited.
This voltage is actually applied to the bit line unless there is a negative translation of level due to the presence of a first selection transistor M6 and a second selection transistor M7 for writing.
Although advantageous from certain viewpoints, this solution is not entirely effective and displays some shortcomings.
As already mentioned, the programming current absorbed by the memory cell can vary from one integrated circuit to another because of the inevitable variations inherent in the production process. It can undergo variations also because of the surrounding conditions in which the circuit is made to operate.
If the current passing through the bit line and hence the output stage of the regulator is actually different from the one called for by the design it follows that the voltage on the bit line will also be wrong or different from that desired.
In addition, since during programming the threshold voltage of the cell tends to rise progressively it follows that the current absorbed by the cell decreases in time. Since with the circuit described above voltage regulation is based on an average programming current, it will not give good results steadily.
A second solution of the known art is shown in FIG. 2 and provides that the drain voltage be supplied by a so-called source-follower piloted by an operational amplifier with appropriate feedback connections.
Even this solution is not free of shortcomings. In particular, this circuit proved to be slow in the reading phase because it seems to increase the capacitance of the bit line.
In addition, it has been observed that with the decrease in the cell dimensions and in particular their actual length, ever closer limits are imposed on drain voltage variation range and this compromises the reliability and performance of the entire memory circuit.
The technical problem underlying the present invention is to conceive a voltage regulator which would supply the bit line constantly at the output with a voltage such as to pursue optimally production process variations.
In other terms, the purpose of the present invention is to conceive a voltage regulator capable of adapting to the actual length of the memory cell and overcoming the limits of the present solutions.
In this manner there is achieved a drain voltage relatively stable as concerns temperature and the circuit production process parameters and variable by .+-.5% with the programming voltage V.sub.PP.
The solution idea underlying the present invention is to insert in the regulator a voltage divider varying with the actual length L of the memory cell by utilizing the resistivity of the material making up the cell gates.
On the basis of this solution idea the technical problem is solved by a voltage regulator which uses a voltage divider to scale down the programming voltage V.sub.PP, IN A WAY WHICH IS DEPENDENT ON DEVICE PARAMETERS, to provide a line programming voltage which varies to compensate for variation in the length (L) of the memory cell. This makes it possible to provide a drain voltage which varies according to the actual length of the memory cell.
A simple voltage divider network using identical elements would not result in any variation of the intermediate voltage with the channel length, and thus would apparently not be suitable for implementing the invention. However, by using different W/L proportions in the individual resistor elements, the ratio of the divider network will change with linewidth variation.
The characteristics and advantages of the voltage regulation circuit in accordance with the present invention are set forth in the description of an embodiment thereof given below by way of non-limiting example with reference to the annexed drawings.